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| 21555 non-transparent pci-to-pci bridge datasheet product features full compliance with the pci local bus specification , revision 2.2, plus: ? pci power management support ? vital product data (vpd) support ? compactpci distributed hot-swap support 3.3-v operation with 5.0-v tolerant i/o selectable asynchronous or synchronous primary and secondary interface clocks concurrent primary and secondary bus operation fully compliant with the advanced configuration power interface (acpi) specification fully compliant with the pci bus power management specification queuing of multiple transactions in either direction 256 bytes of posted write (data and address) buffering in each direction 256 bytes of read data buffering in each direction four delayed transaction entries in each direction two dedicated i2o delayed transaction entries two sets of standard pci configuration registers corresponding to the primary and secondary interface; each set is accessible from either the primary or secondary interface direct offset address translation for downstream memory and i/o transactions hardware enable for secondary bus central functions ieee standard 1149.1 boundary-scan jtag interface four primary interface base address configuration registers for downstream forwarding, with size and prefetchability programmable for all four address ranges three secondary interface address configuration registers specifying local address ranges for upstream forwarding, with size and prefetchability programmable for all three address ranges inverse decoding above the 4 gb address boundary for upstream dacs ability to generate type 0 and type 1 configuration commands on the primary or secondary interface via configuration or i/o csr accesses ability to generate i/o commands on the primary or secondary interface via i/o csr accesses i2o message unit doorbell registers for software generation of primary and secondary bus interrupts, 16 bits per interface eight dwords of scratchpad registers generic own bit (can memory-map) semaphore parallel flash rom interface with primary bus expansion rom base address register serial rom interface secondary bus arbiter support for up to nine external devices at 33 mhz and up to four external devices at 66 mhz (in addition to the 21555) secondary bus clock output for synchronous operation four 32-bit base address configuration registers mapping the 21555 control and status registers (csrs) available in 33 mhz and 66 mhz versions order number: 278320-002 notice: this document contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
ii datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 21555 non-transparent pci-to-pci bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 intel is a trademark or registered trademark of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. datasheet iii contents contents 1.0 introduction ............................................................................................................................... ..... 5 1.1 comparing 21555 and standard pci-to-pci bridge ............................................................. 5 1.2 architectural overview...................................................................................................... .... 8 2.0 pin assignment ...........................................................................................................................10 2.1 pin location list (alphanumeric) ........................................................................................12 2.2 pin signal list (alphanumeric)............................................................................................17 3.0 electrical specifications .............................................................................................................22 3.1 pci electrical specification conformance ..........................................................................22 3.2 absolute maximum ratings ................................................................................................22 3.3 dc specifications ........................................................................................................... ....23 3.4 ac timing specifications .................................................................................................... 23 3.4.1 clock timing specifications ...................................................................................23 3.4.2 pci signal timing specifications ...........................................................................25 3.4.3 reset timing specifications ..................................................................................26 3.4.4 serial rom timing specifications .........................................................................27 3.4.5 parallel rom timing specifications.......................................................................27 3.4.6 jtag timing specifications...................................................................................28 4.0 mechanical specifications ..........................................................................................................29 figures 1 21555 intelligent controller application ...................................................................................... .. 6 2 21555 microarchitecture ....................................................................................................... ........ 9 3 21555 pbga cavity down view.................................................................................................11 4 pci clock signal ac parameter measurements ........................................................................25 5 pci signal timing measurement conditions ..............................................................................25 6 304 pbga (four-layer) package...............................................................................................29 tables 1 21555 and ppb feature comparison...........................................................................................7 2 signal type abbreviations ..................................................................................................... .....10 3 21555 pin location list (alphanumeric) .....................................................................................12 4 21555 pin signal list (alphanumeric).........................................................................................1 7 5 absolute maximum ratings ...................................................................................................... ..22 6 functional operating range.................................................................................................... ...22 7 dc parameters ................................................................................................................. ..........23 8 33 mhz pci clock signal ac parameters..................................................................................24 9 66 mhz pci clock signal ac parameters..................................................................................24 10 33 mhz pci signal timing specifications ..................................................................................26 11 66 mhz pci signal timing specifications ..................................................................................26 12 reset timing specifications .................................................................................................. .....26 13 serial rom timing specifications ............................................................................................. .27 14 parallel rom timing specifications ........................................................................................... 27 15 jtag timing specifications................................................................................................... .....28 contents iv datasheet 16 304-point 4-layer pbga package dimensions ......................................................................... 30 non-transparent ppb datasheet 5 1.0 introduction intel ? s 21555 is a pci peripheral device that performs pci bridging functions for embedded and intelligent i/o applications. the 21555 has a 64-bit primary interface, a 64-bit secondary interface, and 66-mhz capability. the 21554 a related pci peripheral device, has a 64-bit primary interface, a 64-bit secondary interface, and 33-mhz capability. ? the 21555 is a ? non-transparent ? pci-to-pci bridge that acts as a gateway to an intelligent subsystem. it allows a local processor to independently configure and control the local subsystem. the 21555 implements an i2o message unit that enables any local processor to function as an intelligent i/o processor (iop) in an i2o-capable system. because the 21555 is architecture independent, it works with any host and local processors that support a pci bus. this architecture independence enables vendors to leverage existing investments while moving products to pci technology. unlike a transparent pci-to-pci bridge, the 21555 is specifically designed to bridge between two processor domains. the processor domain on the primary interface of the 21555 is also referred to as the host domain, and its processor is the host processor. the secondary bus interfaces to the local domain and the local processor. special features include support of independent primary and secondary pci clocks, independent primary and secondary address spaces, and address translation between the primary (host) and secondary (local) domains. the 21555 enables add-in card vendors to present to the host system a higher level of abstraction than is possible with a transparent pci-to-pci bridge. the 21555 uses a type 0 configuration header, which presents the entire subsystem as a single ? device ? to the host processor. this allows loading of a single device driver for the entire subsystem, and independent local processor initialization and control of the subsystem devices. because the 21555 uses a type 0 configuration header, it does not require hierarchical pci-to-pci bridge configuration code. the 21555 forwards transactions between the primary and secondary pci buses as does a transparent pci-to-pci bridge. in contrast to a transparent pci-to-pci bridge, however, the 21555 can translate the address of a forwarded transaction from a system address to a local address, or vice versa. this mechanism allows the 21555 to hide subsystem resources from the host processor and to resolve any resource conflicts that may exist between the host and local subsystems. the 21555 operates at 3.3 v and is also 5.0-v i/o tolerant. adapter cards designed using the 21555 can be keyed as universal, thus permitting use in either a 5-v or 3-v slot. 1.1 comparing 21555 and standard pci-to-pci bridge the 21555 is functionally similar to a standard pci-to-pci bridge (ppb) in that both provide a connection path between devices attached to two independent pci buses. a 21555 and a ppb allow the electrical loading of devices on one pci bus to be isolated from the other bus while permitting concurrent operation on both buses. because the pci local bus specification restricts pci option cards to a single electrical load, the ability of ppbs and the 21555 to spawn pci buses enables the design of multi device pci option cards. the key difference between a ppb and the 21555 is that the presence of a ppb in a connection path between the host processor and a device is transparent to devices and device drivers, while the presence of the 21555 is not. this difference enables the 21555 to provide features that better support the use of intelligent controllers in the subsystem. non-transparent ppb 6 datasheet it was a primary goal of the pci-to-pci bridge architecture that a ppb be transparent to devices and device drivers. for example, no changes are needed to a device driver when a pci peripheral is located behind a ppb. once configured during system initialization, a ppb operates without the aid of a device driver. a ppb does not require a device driver of its own since it does not have any resources that must be managed by software during run-time. this requirement for transparency forced the usage of a flat addressing model across pci-to-pci bridges. this means that a given physical address exists at only one location in the pci bus hierarchy and that this location may be accessed by any device attached at any point in the pci bus hierarchy. as a consequence, it is not possible for a ppb to isolate devices or address ranges from access by devices on the opposite interface of a ppb. the ppb architecture assumes that the resources of any device in a pci system are configured and managed by the host processor. however, there are applications where the transparency of a pci-to-pci bridge is not desired. for example, figure 1 shows a hypothetical pci add-in card used for an intelligent subsystem application. assume that the local processor on the add-in card is used to manage the resources of the devices attached to the add-in card ? s local pci bus. assume also that it is desirable to restrict access to these same resources from other pci bus masters in the system and from the host processor. in addition, there is a need to resolve address conflicts that may exist between the host system and the local processor. the non transparency of the 21555 is perfectly suited to this kind of configuration, where a transparent pci-to-pci bridge is problematic. because the 21555 is not transparent, the device driver for the add-in card must be aware of the presence of the 21555 and manage its resources appropriately. the 21555 allows the entire subsystem to appear as a single virtual device to the host. this enables configuration software to identify the appropriate driver for the subsystem. with a transparent pci-to-pci bridge, a driver does not need to know about the presence of the bridge and manage its resources. the subsystem appears to the host system as individual pci devices on a secondary pci bus, not as a single virtual device. table 1 shows a comparison between a 21555 and a standard transparent pci-to-pci bridge. figure 1. 21555 intelligent controller application a8826-01 local cpu cpu- pci bridge intel ? 21555 device dram/ rom pci device pci device pci bus host core logic host cpu memory pci device pci bus intelligent subsystem non-transparent ppb datasheet 7 table 1. 21555 and ppb feature comparison feature 21555 pci-to-pci bridge transaction forwarding adheres to ppb ordering rules. adheres to ppb ordering rules. uses posted writes and delayed transactions. uses posted writes and delayed transactions. adheres to ppb transaction error and parity error guidelines, although some errors may be reported differently. adheres to ppb transaction error and parity error guidelines. address decoding base address registers are used to define independent downstream and upstream forwarding windows. ppb base and limit address registers are used to define downstream forwarding windows. inverse decoding is only used for upstream transactions above the 4 gb boundary. inverse decoding for upstream forwarding. address translation supported for both memory and i/o transactions. no translation, a flat address model is assumed. configuration downstream devices are not visible to host. downstream devices are visible to host. does not require hierarchical configuration code (type 0 configuration header). requires hierarchical configuration code (type 1 configuration header). does not respond to type 1 configuration transactions. forwards and converts type 1 configuration transactions. supports configuration access from the secondary bus. implements separate set of configuration registers for the secondary interface. does not support configuration access from the secondary bus. same set of configuration registers is used to control both primary and secondary interfaces. run-time resources includes features such as doorbell interrupts, i2o message unit, and so on, that must be managed by the device driver. typically has only configuration registers; no device driver is required. clocks generates secondary bus clock output. generates one or more secondary bus clock outputs. asynchronous secondary clock input is also supported. secondary bus central functions implements secondary bus arbiter. this function can be disabled. implements secondary bus arbiter. drives secondary bus ad, c/be#, and par during reset. this function can be disabled. drives secondary bus ad, c/be#, and par during reset. non-transparent ppb 8 datasheet 1.2 architectural overview the 21555 consists of the following function blocks: data buffers data buffers include the buffers along with the associated data path control logic. delayed transaction buffers contain the compare functionality for completing delayed transactions. the blocks also contain the watchdog timers associated with the buffers. the data buffers are as follows: four-entry downstream delayed transaction buffer four-entry upstream delayed transaction buffer 256-byte downstream posted write buffer 256-byte upstream posted write buffer 256-byte downstream read data buffer 256-byte upstream read data buffer two downstream i2o delayed transaction entries registers the following register blocks also contain address decode and translation logic, i2o message unit, and interrupt control logic: primary interface header type 0 configuration registers secondary interface header type 0 configuration registers device-specific configuration registers memory and i/o mapped control and status registers control logic the 21555 has the following control logic: primary pci target control logic primary pci master control logic secondary pci target control logic secondary pci master control logic rom interface control logic for both serial and parallel rom connections (interfaces between the rom registers and rom signals) secondary pci bus arbiter interface to secondary bus device request and grant lines, as well as the 21555 secondary master control logic jtag control logic non-transparent ppb datasheet 9 figure 2 shows the 21555 microarchitecture. figure 2. 21555 microarchitecture a7418-01 primary config registers device- specific config registers csr registers secondary config registers jtag rom interface control primary target control primary master control secondary target control secondary master control secondary bus arbiter jtag signals rom interface signals interrupt signals secondary arbiter signals downstream delayed buffer downstream posted write buffer upstream read data buffer downstream read data buffer upstream posted write buffer upstream delayed buffer rimary pci bus secondary pci bus 21555 21555 non-transparent ppb 10 datasheet 2.0 pin assignment this chapter describes the 21555 pin assignment and lists the pins according to location and in alphabetic order. figure 3 shows the 21555 304-point ball grid array (pbga), representing the pins in vertical rows labeled numerically, and horizontal rows labeled alphabetically. table 2 defines the signal type abbreviations used in the signal and pin tables for this specification. table 3 and table 4 use these alphanumerics to identify pin assignments. table 2. signal type abbreviations signal type description i standard input only. o standard output only. ts tristate bidirectional. sts sustained tristate. active low signal must be pulled high for one clock cycle when deasserting. od standard open drain. non-transparent ppb datasheet 11 figure 3. 21555 pbga cavity down view a7436-01 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 a b c d e f g h j k l m n p r t u v w y 21555 aa ab ac 21 22 23 pin 1 corner top view (pin down) non-transparent ppb 12 datasheet 2.1 pin location list (alphanumeric) table 3 lists the 21555 pins in order of location, showing the location code, signal name, and signal type of each pin. figure 3 provides the map for identifying the pin location codes, listed in alphanumeric order in the pbga location column. table 2 defines the signal type abbreviations used in the type column. table 3. 21555 pin location list (alphanumeric) (sheet 1 of 5) pbga location signal name type pbga location signal name type a1 s_req_l[4] i aa7 p_ad[12] ts a2 s_req_l[3] i aa8 p_ad[10] ts a3 s_req_l[1] i aa9 p_cbe_l[0] ts a4 s_ad[29] ts aa10 p_ad[5] ts a5 s_ad[27] ts aa11 vss p a6 s_ad[25] ts aa12 vdd p a7 s_cbe_l[3] ts aa13 vss p a8 s_ad[22] ts aa14 p_cbe_l[7] ts a9 s_ad[20] ts aa15 p_cbe_l[4] ts a10 s_ad[16] ts aa16 vdd p a11 s_frame_l sts aa17 p_ad[58] ts a12 s_devsel_l sts aa18 p_ad[54] ts a13 s_par ts aa19 vss p a14 s_ad[13] ts aa20 vdd p a15 s_ad[10] ts aa21 p_ad[46] ts a16 s_m66ena i aa22 p_ad[42] ts a17 s_cbe_l[0] ts aa23 vdd p a18 s_ad[6] ts ab1 p_ad[16] ts a19 s_ad[3] ts ab2 vss p a20 s_ad[1] ts ab3 p_trdy_l sts a21 s_req64_l sts ab4 p_stop_l sts a22 vdd p ab5 p_serr_l od a23 s_cbe_l[6] ts ab6 p_ad[15] ts aa1 p_ad[18] ts ab7 vss p aa2 vss p ab8 vss p aa3 p_ad[17] ts ab9 p_ad[8] ts aa4 vss p ab10 p_ad[6] ts aa5 vdd p ab11 vdd p aa6 p_par ts ab12 p_ad[1] ts non-transparent ppb datasheet 13 ab13 p_ad[0] ts b4 vdd p ab14 p_cbe_l[6] ts b5 s_ad[26] ts ab15 p_ad[63] ts b6 s_ad[24] ts ab16 p_ad[60] ts b7 s_idsel i ab17vsspb8vssp ab18 p_ad[55] ts b9 s_ad[18] ts ab19 p_ad[53] ts b10 vss p ab20 p_ad[51] ts b11 vss p ab21 p_ad[48] ts b12 s_trdy_l sts ab22 vss p b13 s_serr_l od ab23 vdd p b14 s_ad[14] ts ac1 vdd p b15 s_ad[12] ts ac2 vdd p b16 vdd p ac3 p_frame_l sts b17 s_ad[9] ts ac4 p_devsel_l sts b18 s_ad[7] ts ac5 p_perr_l sts b19 s_ad[4] ts ac6 p_cbe_l[1] ts b20 vdd p ac7 p_ad[14] ts b21 vss p ac8 p_ad[11] ts b22 vss p ac9 p_m66ena i b23 vdd p ac10 p_ad[7] ts c1 s_req_l[6] i ac11 p_ad[3] ts c2 s_req_l[7] i ac12 p_ad[2] ts c3 s_req_l[2] i ac13 p_ack64_l sts c4 s_ad[31] ts ac14 p_cbe_l[5] ts c5 s_ad[28] ts ac15 p_ad[61] ts c6 vss p ac16 p_ad[59] ts c7 s_ad[23] ts ac17 p_ad[56] ts c8 s_ad[21] ts ac18 vdd p c9 s_ad[17] ts ac19 p_ad[52] ts c10 vdd p ac20 p_ad[50] ts c11 s_irdy_l sts ac21 p_ad[47] ts c12 s_stop_l sts ac22 p_ad[45] ts c13 s_perr_l sts ac23 p_ad[44] ts c14 s_ad[15] ts b1 vdd p c15 vdd p b2 vss p c16 vss p b3 s_req_l[0] i c17 vss p table 3. 21555 pin location list (alphanumeric) (sheet 2 of 5) pbga location signal name type pbga location signal name type non-transparent ppb 14 datasheet c18 s_ad[5] ts f1 s_gnt_l[6] ts c19 s_ad[2] ts f2 s_gnt_l[7] ts c20 s_ack64_l sts f3 s_gnt_l[5] ts c21 s_cbe_l[5] ts f4 vss p c22 s_par64 ts f20 vss p c23 s_cbe_l[4] ts f21 vss p d1 s_gnt_l[1] ts f22 s_ad[56] ts d2 s_gnt_l[2] ts f23 s_ad[57] ts d3 s_req_l[8] i g1 s_gnt_l[8] ts d4 s_req_l[5] i g2 vss p d5 s_ad[30] ts g3 s_clk i d6 vdd p g4 s_clk_o o d7 vdd p g20 vdd p d8 vss p g21 s_ad[53] ts d9 s_ad[19] ts g22 s_ad[54] ts d10 vdd p g23 s_ad[55] ts d11 s_cbe_l[2] ts h1 s_rst_l o d12 vss p h2 s_inta_l od d13 s_cbe_l[1] ts h3 tdi i d14 vdd p h4 vdd p d15 s_ad[11] ts h20 vdd p d16 vss p h21 s_ad[50] ts d17 s_ad[8] ts h22 s_ad[51] ts d18 vdd p h23 s_ad[52] ts d19 s_ad[0] ts j1 tdo o d20 s_cbe_l[7] ts j2 tck i d21 vss p j3 trst_l i d22 s_ad[61] ts j4 tms i d23 s_ad[62] ts j20 vdd p e1 s_rst_in_l i j21 s_ad[47] ts e2 s_gnt_l[4] ts j22 s_ad[48] ts e3 s_gnt_l[3] ts j23 s_ad[49] ts e4 s_gnt_l[0] ts k1 sr_cs o e20 s_ad[63] ts k2 pr_ad[7] ts e21 s_ad[60] ts k3 pr_ad[6] ts e22 s_ad[58] ts k4 vss p e23 s_ad[59] ts k20 vss p table 3. 21555 pin location list (alphanumeric) (sheet 3 of 5) pbga location signal name type pbga location signal name type non-transparent ppb datasheet 15 k21 s_ad[45] ts r3 vdd p k22 vss p r4 p_clk i k23 s_ad[46] ts r20 l_stat ts l1 pr_ad[4] ts r21 s_ad[33] ts l2 pr_ad[3] ts r22 s_ad[32] ts l3 pr_ad[2] ts r23 s_pme_l i l4 pr_ad[5] ts t1 p_ad[30] ts l20 s_ad[44] ts t2 p_ad[31] ts l21 s_ad[42] ts t3 p_req_l ts l22 s_ad[41] ts t4 vdd p l23 s_ad[43] ts t20 vdd p m1 pr_ad[0] ts t21 s_vio i m2 pr_rd_l o t22 p_enum_l od m3 pr_ad[1] ts t23 p_pme_l od m4 vdd p u1 p_ad[27] ts m20 vdd p u2 p_ad[29] ts m21 vdd p u3 vss p m22 s_ad[40] ts u4 p_ad[28] ts m23 vss p u20 p_par64 ts n1 pr_wr_l o u21 p_vio i n2 pr_ale_l o u22 vdd p n3 pr_cs_l / pr_rdy o/i u23 p_ad[32] ts n4 pr_clk o v1 p_ad[25] ts n20 s_ad[36] ts v2 p_ad[26] ts n21 s_ad[39] ts v3 p_ad[24] ts n22 s_ad[38] ts v4 vss p n23 s_ad[37] ts v20 vss p p1 p_rst_l i v21 p_ad[35] ts p2 p_inta_l od v22 p_ad[33] ts p3 scan_ena i v23 p_ad[34] ts p4 vss p w1 p_idsel i p20 vss p w2 p_cbe_l[3] ts p21 s_ad[35] ts w3 p_ad[23] ts p22 s_ad[34] ts w4 p_ad[20] ts p23 vss p w20 p_ad[40] ts r1 p_gnt_l i w21 p_ad[38] ts r2 vss p w22 p_ad[36] ts table 3. 21555 pin location list (alphanumeric) (sheet 4 of 5) pbga location signal name type pbga location signal name type non-transparent ppb 16 datasheet w23 p_ad[37] ts y12 vss p y1 p_ad[21] ts y13 p_req64_l sts y2 p_ad[22] ts y14 vdd p y3 p_ad[19] ts y15 p_ad[62] ts y4 p_cbe_l[2] ts y16 vss p y5 p_irdy_l sts y17 p_ad[57] ts y6 vdd p y18 vdd p y7 p_ad[13] ts y19 p_ad[49] ts y8 vss p y20 p_ad[43] ts y9 p_ad[9] ts y21 p_ad[41] ts y10 vdd p y22 p_ad[39] ts y11 p_ad[4] ts y23 vss p table 3. 21555 pin location list (alphanumeric) (sheet 5 of 5) pbga location signal name type pbga location signal name type non-transparent ppb datasheet 17 2.2 pin signal list (alphanumeric) table 4 lists the 21555 signals in alphanumeric order, showing the name, location code, and type of each signal. figure 3 provides the map for identifying the pin location codes that are listed under pbga location column. table 2 defines the signal type abbreviations used in the type column. table 4. 21555 pin signal list (alphanumeric) (sheet 1 of 5) signal name pbga location type signal name pbga location type l_stat r20 ts p_ad[27] u1 ts p_ack64_l ac13 sts p_ad[28] u4 ts p_ad[0] ab13 ts p_ad[29] u2 ts p_ad[1] ab12 ts p_ad[30] t1 ts p_ad[2] ac12 ts p_ad[31] t2 ts p_ad[3] ac11 ts p_ad[32] u23 ts p_ad[4] y11 ts p_ad[33] v22 ts p_ad[5] aa10 ts p_ad[34] v23 ts p_ad[6] ab10 ts p_ad[35] v21 ts p_ad[7] ac10 ts p_ad[36] w22 ts p_ad[8] ab9 ts p_ad[37] w23 ts p_ad[9] y9 ts p_ad[38] w21 ts p_ad[10] aa8 ts p_ad[39] y22 ts p_ad[11] ac8 ts p_ad[40] w20 ts p_ad[12] aa7 ts p_ad[41] y21 ts p_ad[13] y7 ts p_ad[42] aa22 ts p_ad[14] ac7 ts p_ad[43] y20 ts p_ad[15] ab6 ts p_ad[44] ac23 ts p_ad[16] ab1 ts p_ad[45] ac22 ts p_ad[17] aa3 ts p_ad[46] aa21 ts p_ad[18] aa1 ts p_ad[47] ac21 ts p_ad[19] y3 ts p_ad[48] ab21 ts p_ad[20] w4 ts p_ad[49] y19 ts p_ad[21] y1 ts p_ad[50] ac20 ts p_ad[22] y2 ts p_ad[51] ab20 ts p_ad[23] w3 ts p_ad[52] ac19 ts p_ad[24] v3 ts p_ad[53] ab19 ts p_ad[25] v1 ts p_ad[54] aa18 ts p_ad[26] v2 ts p_ad[55] ab18 ts non-transparent ppb 18 datasheet p_ad[56] ac17 ts pr_ad[2] l3 ts p_ad[57] y17 ts pr_ad[3] l2 ts p_ad[58] aa17 ts pr_ad[4] l1 ts p_ad[59] ac16 ts pr_ad[5] l4 ts p_ad[60] ab16 ts pr_ad[6] k3 ts p_ad[61] ac15 ts pr_ad[7] k2 ts p_ad[62] y15 ts pr_ale_l n2 o p_ad[63] ab15 ts pr_clk n4 o p_cbe_l[0] aa9 ts pr_cs_l / pr_rdy n3 o/i p_cbe_l[1] ac6 ts pr_rd_l m2 o p_cbe_l[2] y4 ts pr_wr_l n1 o p_cbe_l[3] w2 ts p_vio u21 i p_cbe_l[4] aa15 ts s_ack64_l c20 sts p_cbe_l[5] ac14 ts s_ad[0] d19 ts p_cbe_l[6] ab14 ts s_ad[1] a20 ts p_cbe_l[7] aa14 ts s_ad[2] c19 ts p_clk r4 i s_ad[3] a19 ts p_devsel_l ac4 sts s_ad[4] b19 ts p_enum_l t22 od s_ad[5] c18 ts p_frame_l ac3 sts s_ad[6] a18 ts p_gnt_l r1 i s_ad[7] b18 ts p_idsel w1 i s_ad[8] d17 ts p_inta_l p2 od s_ad[9] b17 ts p_irdy_l y5 sts s_ad[10] a15 ts p_m66ena ac9 i s_ad[11] d15 ts p_par aa6 ts s_ad[12] b15 ts p_par64 u20 ts s_ad[13] a14 ts p_perr_l ac5 sts s_ad[14] b14 ts p_pme_l t23 od s_ad[15] c14 ts p_req_l t3 ts s_ad[16] a10 ts p_req64_l y13 sts s_ad[17] c9 ts p_rst_l p1 i s_ad[18] b9 ts p_serr_l ab5 od s_ad[19] d9 ts p_stop_l ab4 sts s_ad[20] a9 ts p_trdy_l ab3 sts s_ad[21] c8 ts pr_ad[0] m1 ts s_ad[22] a8 ts pr_ad[1] m3 ts s_ad[23] c7 ts table 4. 21555 pin signal list (alphanumeric) (sheet 2 of 5) signal name pbga location type signal name pbga location type non-transparent ppb datasheet 19 s_ad[24] b6 ts s_ad[61] d22 ts s_ad[25] a6 ts s_ad[62] d23 ts s_ad[26] b5 ts s_ad[63] e20 ts s_ad[27] a5 ts s_cbe_l[0] a17 ts s_ad[28] c5 ts s_cbe_l[1] d13 ts s_ad[29] a4 ts s_cbe_l[2] d11 ts s_ad[30] d5 ts s_cbe_l[3] a7 ts s_ad[31] c4 ts s_cbe_l[4] c23 ts s_ad[32] r22 ts s_cbe_l[5] c21 ts s_ad[33] r21 ts s_cbe_l[6] a23 ts s_ad[34] p22 ts s_cbe_l[7] d20 ts s_ad[35] p21 ts s_clk g3 i s_ad[36] n20 ts s_clk_o g4 o s_ad[37] n23 ts s_devsel_l a12 sts s_ad[38] n22 ts s_frame_l a11 sts s_ad[39] n21 ts s_gnt_l[0] e4 ts s_ad[40] m22 ts s_gnt_l[1] d1 ts s_ad[41] l22 ts s_gnt_l[2] d2 ts s_ad[42] l21 ts s_gnt_l[3] e3 ts s_ad[43] l23 ts s_gnt_l[4] e2 ts s_ad[44] l20 ts s_gnt_l[5] f3 ts s_ad[45] k21 ts s_gnt_l[6] f1 ts s_ad[46] k23 ts s_gnt_l[7] f2 ts s_ad[47] j21 ts s_gnt_l[8] g1 ts s_ad[48] j22 ts s_idsel b7 i s_ad[49] j23 ts s_inta_l h2 od s_ad[50] h21 ts s_irdy_l c11 sts s_ad[51] h22 ts s_m66ena a16 i s_ad[52] h23 ts s_par a13 ts s_ad[53] g21 ts s_par64 c22 ts s_ad[54] g22 ts s_perr_l c13 sts s_ad[55] g23 ts s_pme_l r23 i s_ad[56] f22 ts s_req_l[0] b3 i s_ad[57] f23 ts s_req_l[1] a3 i s_ad[58] e22 ts s_req_l[2] c3 i s_ad[59] e23 ts s_req_l[3] a2 i s_ad[60] e21 ts s_req_l[4] a1 i table 4. 21555 pin signal list (alphanumeric) (sheet 3 of 5) signal name pbga location type signal name pbga location type non-transparent ppb 20 datasheet s_req_l[5] d4 i vdd d7 p s_req_l[6] c1 i vdd d10 p s_req_l[7] c2 i vdd d14 p s_req_l[8] d3 i vdd d18 p s_req64_l a21 sts vdd g20 p s_rst_in_l e1 i vdd h4 p s_rst_l h1 o vdd h20 p s_serr_l b13 od vdd j20 p s_stop_l c12 sts vdd m4 p s_trdy_l b12 sts vdd m20 p scan_ena p3 i vdd m21 p sr_cs k1 o vdd r3 p s_vio t21 i vdd t4 p tck j2 i vdd t20 p tdi h3 i vdd u22 p tdo j1 o vdd y6 p tms j4 i vdd y10 p trst_l j3 i vdd y14 p vdd a22 p vdd y18 p vdd aa5 p vss aa2 p vdd aa12 p vss aa4 p vdd aa16 p vss aa11 p vdd aa20 p vss aa13 p vdd aa23 p vss aa19 p vdd ab11 p vss ab2 p vdd ab23 p vss ab7 p vdd ac1 p vss ab8 p vdd ac2 p vss ab17 p vdd ac18 p vss ab22 p vdd b1 p vss b2 p vdd b4 p vss b8 p vdd b16 p vss b10 p vdd b20 p vss b11 p vdd b23 p vss b21 p vdd c10 p vss b22 p vdd c15 p vss c6 p vdd d6 p vss c16 p table 4. 21555 pin signal list (alphanumeric) (sheet 4 of 5) signal name pbga location type signal name pbga location type non-transparent ppb datasheet 21 vss c17 p vss m23 p vss d8 p vss p4 p vss d12 p vss p20 p vss d16 p vss p23 p vss d21 p vss r2 p vss f4 p vss u3 p vss f20 p vss v4 p vss f21 p vss v20 p vss g2 p vss y8 p vss k4 p vss y12 p vss k20 p vss y16 p vss k22 p vss y23 p table 4. 21555 pin signal list (alphanumeric) (sheet 5 of 5) signal name pbga location type signal name pbga location type non-transparent ppb 22 datasheet 3.0 electrical specifications this section specifies the following electrical behavior of the 21555: pci electrical conformance. absolute maximum ratings. dc specifications. ac timing specifications. 3.1 pci electrical specification conformance the 21555 pci pins conform to the basic set of pci electrical specifications in the pci local bus specification , revision 2.2. see that document for a complete description of the pci i/o protocol and pin ac specifications. 3.2 absolute maximum ratings the 21555 is specified to operate at a maximum frequency of 33 mhz or 66 mhz if 66 mhz capable, at a junction temperature (t j ) not to exceed 125 table 5. absolute maximum ratings parameter minimum maximum junction temperature, t j ? 125 v cc ? 4.3 v maximum voltage applied to signal pins ? 5.5 v maximum power, p wc ? 3.0 w storage temperature range, t stg ? 55 table 6. functional operating range parameter minimum maximum supply voltage, v cc 3.0 v 3.6 v operating ambient temperature, t a 0 non-transparent ppb datasheet 23 3.3 dc specifications table 7 defines the dc parameters met by all 21555 signals under the conditions of the functional operating range. note: in table 7 , currents into the chip (chip sinking) are denoted as positive (+) current. currents from the chip (chip sourcing) are denoted as negative ( ? ) current. 3.4 ac timing specifications the next sections specify the ac characteristics met by all 21555 signals under the conditions of the functional operating range: clock timing. pci signal timing. reset timing. serial rom timing. parallel rom timing. jtag timing. 3.4.1 clock timing specifications the ac specifications consist of input requirements and output responses. the input requirements consist of setup and hold times, pulse widths, and high and low times. the output responses are delays from clock to signal. the ac specifications are defined separately for each clock domain within the 21555. table 7. dc parameters symbol parameter condition minimum maximum unit v cc supply voltage ? 3.0 3.6 v v il low-level input voltage a a. guarantees meeting the specification for the 5-v signaling environment. ?? 0.5 0.3 v cc v v ih high-level input voltage a ? 0.5 v cc v io + 0.5 v v v ol low-level output voltage b b. for 3.3-v signaling environment. i out = 1500 a ? 0.1 v cc v v ol5v low-level output voltage c c. for 5-v signaling environment. i out = 6 ma ? 0.55 v v oh high-level output voltage b i out = ? 500 a 0.9 v cc ? v v oh5v high-level output voltage c i out = ? 2 ma 2.4 ? v i il low-level input leakage current a,d d. input leakage currents include high-z output leakage for all bidirectional buffers with tristate outputs. 0 non-transparent ppb datasheet 25 3.4.2 pci signal timing specifications figure 5 and tables 10 and 11 show the pci signal timing specifications. figure 4. pci clock signal ac parameter measurements a7834-01 v t1 t high p_clk s_clk v t2 v t3 t cyc t cyc t r t f t low v t1 t high t skew v t2 t r t f v t3 t skew t low notes: t t1 - 2.0 v for 5-v signals; 0.5 v cc for 3.3-v clocks t t2 - 1.5 v for 5-v signals; 0.4 v cc for 3.3-v clocks t t3 - 0.8 v for 5-v signals; 0.3 v cc for 3.3-v clocks figure 5. pci signal timing measurement conditions a7835-01 v test t val t inval t on t off t su t h clk valid output input note: t test - 1.5 v for 5-v signals; 0.4 v cc for 3.3-v signals valid non-transparent ppb 26 datasheet 3.4.3 reset timing specifications table 12 shows the reset timing specifications for p_rst_l and s_rst_l. table 10. 33 mhz pci signal timing specifications symbol parameter minimum maximum unit t val clk to signal valid delay ? bused signals a,b,c a. see figure 5 . b. all primary interface signals are synchronized to p_clk. all secondary interface signals are synchronized to s_clk. c. point-to-point signals are p_req_l, s_req_l[8:0], p_gnt_l, and s_gnt_l[8:0]. bused signals are p_ad, p_cbe_l, p_par, p_par64, p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, s_ad, s_cbe_l, s_par, s_par64, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l, and s_idsel. 211ns t val(ptp) clk to signal valid delay ? point-to-point a,b,c 212ns t on float to active delay a,b 2 ? ns t off active to float delay a,b ? 28 ns t su input setup time to clk ? bused signals a,b,c 7 ? ns t su(ptp) input setup time to clk ? point-to-point a,b,c 10, 12 ? ns t h input signal hold time from clk a,b 0 ? ns table 11. 66 mhz pci signal timing specifications symbol parameter minimum maximum unit t val clk to signal valid delay ? bused signals a,b,c a. see figure 5 . b. all primary interface signals are synchronized to p_clk. all secondary interface signals are synchronized to s_clk. c. point-to-point signals are p_req_l, s_req_l[8:0], p_gnt_l, and s_gnt_l[8:0]. bused signals are p_ad, p_cbe_l, p_par, p_par64, p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, s_ad, s_cbe_l, s_par, s_par64, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l, and s_idsel. 26ns t val(ptp) clk to signal valid delay ? point-to-point a,b,c 26ns t on float to active delay a,b 2 ? ns t off active to float delay a,b ? 14 ns t su input setup time to clk ? bused signals a,b 3 ? ns t su(ptp) input setup time to clk ? point-to-point a,b 5 ? ns t h input signal hold time from clk a,b 0 ? ns table 12. reset timing specifications (sheet 1 of 2) symbol parameter minimum maximum unit t rst p_rst_l active time after power stable 1 ? s t rst-clk p_rst_l active time after p_clk stable 100 ? s t rst-off p_rst_l active-to-output float delay ? 40 ns t srst s_rst_l active after p_rst_l assertion ? 40 ns t srst-on s_rst_l active time after s_clk stable 100 ? s t dsrst s_rst_l deassertion after p_rst_l deassertion 0 25 cycles ? p_rst_l slew rate a 50 ? mv/ns non-transparent ppb datasheet 27 3.4.4 serial rom timing specifications table 13 shows the serial rom timing specifications. 3.4.5 parallel rom timing specifications table 14 shows the parallel rom timing specifications. t rrsus s_req64_l asserted to s_rst_l deasserted 10*t cyc ? ns a t rrval s_rst_l to s_req64_l deasserted delay time 0 t cyc ? ns a t rrsu req64# to rst# deasserting setup time t cyc ? ns t rrh req64# from rst# deasserting hold time 0 50 ns a. applies to rising (deasserting) edge only. table 12. reset timing specifications (sheet 2 of 2) symbol parameter minimum maximum unit table 13. serial rom timing specifications symbol parameter minimum maximum unit t scval pclk to pr_ad[0] serial rom clock valid ? 14 ns t son pr_ad float to active delay 2 ? ns t soff pr_ad active to float delay ? 28 ns t ssu pr_ad[1] di to pr_ad[0] serial rom clock setup time 400 ? ns t sh pr_ad[1] to pr_ad[0] serial rom clock hold time 20 ? ns t smcs sr_cs minimum low time 400 ? ns t scyc pr_ad[0] serial rom clock cycle time 1000 ? ns table 14. parallel rom timing specifications symbol parameter minimum maximum unit t pas pr_ale_l setup to pr_clk rising 30 ? ns t pcc pr_clk cycle time 60 ? ns t pacs pr_ale_l rising to pr_cs_l falling 25 ? ns t pcsl pr_cs_l low 200 ? ns t pcrw pr_cs_l falling to pr_rd_l or pr_wr_l falling 25 ? ns t prs pr_ad setup time to pr_rd_l rising 180 ? ns t prh pr_ad hold time from pr_rd_l rising 0 ? ns t prv pr_clk rising to pr_ad valid 0 15 ns non-transparent ppb 28 datasheet 3.4.6 jtag timing specifications table 15 shows the jtag timing specifications. table 15. jtag timing specifications symbol parameter minimum maximum unit t jr tck frequency 0 5 mhz t jp tck period 200 ? ns t glt tck low time 100 ? ns t jrt tck rise time a a. measured between 0.8 v and 2.0 v. ? 10 ns t gft tck fall time b b. measured between 2.0 v and 0.8 v. ? 10 ns t js tdi, tms setup time to tck rising edge 10 ? ns t jh tdi, tms hold time from tck rising edge 25 ? ns t jd tdo valid delay from tck falling edge c c. c 1 =50 pf. ? 30 ns t jfd tdo float delay from tck falling edge ? 30 ns non-transparent ppb datasheet 29 4.0 mechanical specifications the 21555 is contained in an industry-standard 304 pbga, a four-layer plastic ball grid array package, as shown in figure 6 . figure 6. 304 pbga (four-layer) package a7523-01 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 a b c d e f g h j k l m n p r t u v w y 21555 aa ab ac 21 22 23 pin 1 corner pin 1 i.d. d d1 _ b _ _ a _ e1 e _ c _ _ basic dimension _ reference dimension ( ) a c s b aaa notes: c bbb / 0.30 s a 2 a a 1 c pin 1 corner e ( j ) ( i ) 30 o b / s top view bottom view / / e non-transparent ppb 30 datasheet table 16 lists the package dimensions in millimeters. table 16. 304-point 4-layer pbga package dimensions symbol dimension minimum value nominal value maximum value e ball pitch ? 1.27 bsc a a. ansi y14.5m-1982 american national standard dimensioning and tolerancing, section 1.3.2, defines basic dimension (bsc) as: a numerical value used to describe the theoretically exact size, profile, orientation, or location of a feature or da tum target. it is the basis from which permissible variations are established by tolerances on other dimensions, in notes, or in f ea- ture control frames. ? a overall package height 2.12 2.33 2.54 a 1 package standoff height 0.50 0.60 0.70 a 2 encapsulation thickness 1.12 1.17 1.22 b ball diameter 0.60 0.76 0.90 c substrate thickness 0.56 reference b b. the value for this measurement is for reference only. aaa coplanarity ?? 0.2 bbb overall package planarity ?? 0.15 d overall package width 30.80 31.00 31.20 d 1 overall encapsulation width ? 26.00 26.70 e overall package width 30.80 31.00 31.20 e 1 overall encapsulation width ? 26.00 26.70 i location of first row ( x -direction) ? 1.53 reference b ? j location of first row ( y -direction) ? 1.53 reference b ? 21555 non-transparent pci-to- pci bridge specification update december 2002 notice: the 21555 may contain design defects or errors known as errata. characterized errata that may cause the 21555?s behavior to deviate from published specifications are documented in this specification update. order number: 278337-008 ii 21555 non-transparent pci-to-pci bridge specification update information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel ? s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel ? s website at http://www.intel.com. copyright ? intel corporation, 2002. intel is a trademark or registered trademark of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. 21555 non-transparent pci-to-pci bridge specification update iii contents revision history ......................................................................................... 5 preface....................................................................................................... 7 summary table of changes....................................................................... 8 identification information...........................................................................11 errata ....................................................................................................... 12 specification changes ............................................................................. 14 specification clarifications ....................................................................... 15 documentation changes ......................................................................... 16 21555 non-transparent pci-to-pci bridge specification update 5 documentation changes revision history date version description 12/19/02 008 the following changes have been made to this document: 21555 bridge steppings have changed to a3. markings have been updated as well. see ? markings ? on page 11 . added related document to ? affected documents/related documents ? on page 7 . status for errata 1 and 2 are changed to fixed. see ? errata ? on page 9 . specification change - 21555 bridge pci compliancy now at version 2.3. see ? specification changes ? on page 9 . documentation changes - data sheet and user manual include 2.3 compliance information. see ? added section 3.1.1 pci local bus compliance ? on page 22 . and ? change to tables 61 and 62 in section 16.5.2 ? on page 22 . 6/12/02 007 added errata 2. 4/12/02 006 added errata 1. 6/11/01 005 corrected pbga package description from 2-layer to 4-layer within this document. 6/7/01 004 documentation changes: (see page 9 ) replaced last row of table 2-3. see section 14 on page 21. changed l_stat description in section 11-5. see section 15 on page 22 . 5/24/01 003 documentation changes: (see page 8 ) added markings table on page 11 . insert reference to 21554 for improved accuracy. see section 3 on page 16 . remove misplaced sections from chapter 4. see section 4 on page 17. remove unnecessary parenthetical phrase. see section 5 on page 19 . change p_clk and s_clk signal description. see section 6 on page 19 . remove incorrect sentence from hot swap input pin description. see section 7 on page 19 . change or remove three (3) references to the 21554. see section 8 on page 19. update d7:d6 byte offset descriptions. see section 9 on page 20. remove three references to cls=4. see section 10 on page 20 . additional information about jtag pin termination requirements. see section 11 on page 20 . emphasize special handling of the jtag tms signal for hot insertion applications.see section 12 on page 20 . changed section 12.2.1 and jtag description. see section 13 on page 21 . 9/15/00 002 added specification change to pbga package dimensions for coplanarity maximum value. 2/21/00 001 this new specification update document contains: one specification change that announces coplanarity value changes. two documentation changes that: correct the jtag timing specifications. correct the coplanarity values in the datasheet document. 21555 non-transparent pci-to-pci bridge specification update 7 documentation changes preface this document is an update to the specifications contained in the affected documents/related documents table below. this document is a compilation of device and documentation errata, specification clarifications and changes. it is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. information types defined in nomenclature are consolidated into the specification update and are no longer published in other documents. this document may also contain information that was not previously published. affected documents/related documents nomenclature errata are design defects or errors. these may cause the 21555?s behavior to deviate from published specifications. hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. specification changes are modifications to the current published specifications. these changes will be incorporated in any new release of the specification. specification clarifications describe a specification in greater detail or further highlight a specification?s impact to a complex design situation. these clarifications will be incorporated in any new release of the specification. documentation changes include typos, errors, or omissions from the current published specifications. these will be incorporated in any new release of the specification. note: errata remain in the specification update throughout the product?s lifecycle, or until a particular stepping is no longer commercially available. under these circumstances, errata removed from the specification update are archived and available upon request. specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.). title order 21555 non-transparent pci-to-pci bridge advance information datasheet (specification) 278320 21555 non-transparent pci-to-pci bridge advance information user ? s manual 278321 21555aa/ba and 21555ab/bb differences application note 278669 8 21555 non-transparent pci-to-pci bridge specification update documentation changes summary table of changes the following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the 21555 non-transparent pci-to-pci bridge product. intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. this table uses the following notations: codes used in summary table stepping x: errata exists in the stepping indicated. specification change or clarification that applies to this stepping. (no mark) or (blank box): this erratum is fixed in listed stepping or specification change does not apply to listed stepping. page (page): page location of item in this document. status doc: document change or update will be implemented. fix: this erratum is intended to be fixed in a future step of the component. fixed: this erratum has been previously fixed. nofix: there are no plans to fix this erratum. row change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. 21555 non-transparent pci-to-pci bridge specification update 9 documentation changes errata no. steppings page status errata a2 a3 1. x 12 fixed ? 21555aa/ba boundary scan implementation is not compliant with ieee 1149.1 ? 2. x 13 fixed ? 21555aa/ba i2o circuitry will not work asynchronously ? specification changes no. steppings page status specification changes a2 a3 1 xx 14 doc change pbga package dimensions for coplanarity changed from maximum value 0.15 mm to maximum value 0.2 mm. 2 x 14 doc change pci 2.3 compliance specification clarifications no. steppings page status specification clarifications ### none for this revision of this specification update. documentation changes no. document revision page documentation changes 1 278320-001 16 datasheet ? section 3.4.6: jtag timing specifications ? 2 278320-001 16 datasheet ? section 4.0, table 16, 304-point 4-layer pbga package dimensions ? 3 278321-001 16 user ? s manual: ? add a specific reference to 21554 to first introduction paragraph ? 4 278321-001 17 user ? s manual: ? remove sections 4.2 through 4.2.4 to section 2.3.4 ? 5 278321-001 19 user ? s manual: ? remove unnecessary parenthetical phrase from rom interface signal description ? 6 278321-001 19 user ? s manual: ? table 10-1 p_clk and s_clk descriptions need correction and updating ? 7 278321-001 19 user ? s manual: ? section 11.2.1, hot insertion input pin description change ? 8 278321-001 19 user ? s manual: ? remove or change 3 incorrect references to the 21554 ? 9 278321-001 20 user ? s manual: ? section 16.1byte offset of d7:d6 needs updating ? 10 21555 non-transparent pci-to-pci bridge specification update documentation changes 10 278321-001 20 user ? s manual: ? remove reference to cls=4 ? 11 278321-001 20 user ? s manual: ? jtag action during hot insertion ? 12 278321-001 20 user ? s manual: ? internal and external signal terminations ? 13 278321-001 21 user ? s manual: ? change to initialization section 12.2.1 and jtag description ? 14 278321-001 21 user ? s manual: ? change to chapter 2, table 2-3 p_req64_l description ? 15 278321-001 22 user ? s manual: ? change to section 11.5 l_stat pin description ? 16 278320-001 22 data sheet: ? added section 3.1.1 pci local bus compliance ? 16 278321-001 22 user ? s manual: ? change to tables 61 and 62 in section 16.5.2 ? documentation changes 21555 non-transparent pci-to-pci bridge specification update 11 documentation changes identification information markings package markings rev_id register value 1 1. identified in a pci system by reading the value in the rev_id register. speed (mhz) stepping intel fw21555aa 02h 33 a2 intel fw21555ba 02h 66 a2 intel FW21555AB 03h 33 a3 intel fw21555bb 03h 66 a3 12 21555 non-transparent pci-to-pci bridge specification update documentation changes errata 1. 21555aa/ba boundary scan implementation is not compliant with ieee 1149.1 problem: there is a one cycle delay before valid bsdl data is pushed out to the pins. the problem is due to an incorrect inversion in the equation that generates the jtag update. implication: the parallel output data from any bi-directional pins, purely output pins or control cells, will be driven out exactly one clock after the update state. this is in violation of the ieee1149.1 speci- fication. workaround: although the 21555 jtag implementation is non-compliant, it may still be usable for test purposes if the following considerations are understood: workaround 1: in-circuit testers should test for the parallel output data to be on the pins of the chip, at least one clock after the update state. typically automated test pattern generator (atpg) test vectors will test for this state upon exiting the update state. this test should be delayed one clock from the atpg vectors. also, in-circuit testers should ensure that data is driven onto pins of the 21555, one clock after update, to avoid any potential of back driving a pin. workaround 2: standalone boundary scan testers and in-circuit testers performing chained boundary scan tests, should understand that the parallel output update data, being delayed by one clock, may cause bus contention and back driving during that one clock period, assuming the vectors change bus driving sources in one vector. this is because in chained boundary scan tests, all components execute tap instructions in parallel (or lock step), and vector generation algorithms optimize the number of vectors. to understand the potential issue in detail, refer to the diagram below. node 1 is a bi-directional node, with u1.1 and u2.2 connected as shown. assuming that u1 is an ieee1149.1 compliant device, that u2 is the 21555, and that the control cells of the 21555 were set during the vectors to enable the driver of u2.2 to drive to u1.1 (receiver). when switching drivers from u2 to u1, u2 should tri-state its driver prior to, or at the same time as, u1 enables its driver. since the 21555 updates its parallel outputs one clock late and the control cells which enable u2 ? s drivers are parallel outputs which again updates one clock cycle late then u2.2, which will be driving at the same time u1.1 is driving. this contention will happen for one tck cycle, until u2 updates its parallel outputs. the period of this contention is dependent on the tck frequency rate. a remedy to the 21555 ? s late update is to ensure the chained boundary scan tester ? s vectors do not switch bus driver directions in one vector. this means that one vector should disable u2 ? s driver, and the next vector should enable u1 ? s driver. atpg vectors typically are not manually manageable in this way and this requirement may force an engineer ? s manual intervention. no single stepping of test clock through the tap state machine should be allowed with the 21555 in the boundary scan chain. the resulting contention would increase the potential back drive time, increasing the possibility of device damage. 21555 non-transparent pci-to-pci bridge specification update 13 documentation changes status: fixed.this behavior has been corrected in the 21555ab/bb step a3 device. 2. 21555aa/ba i 2 o circuitry will not work asynchronously problem: the i 2 o circuitry does not function properly in asynchronous mode. the root cause of this problem is the synchronization logic between the primary and secondary clock domains - they are incorrectly wired. implication: the i 2 o circuitry will not function in asynchronous mode and can hang the system. workaround: there is no workaround for applications that require asynchronous operation of the i 2 o circuitry. although the 21555 i 2 o circuitry is improperly implemented for asynchronous operation, the device will work properly in synchronous mode. status: fixed. this behavior has been corrected in the 21555ab/bb step a3 device. note: no changes were made to the bsdl file when correcting this problem. figure 1. node boundary a9874-01 u2-21555* u1-abc *note: intel ? 21555 bridge design node 1 12 14 21555 non-transparent pci-to-pci bridge specification update documentation changes specification changes 1. pbga package dimensions for coplanarity changed from maximum value 0.15 mm to maximum value 0.2 mm. per pcn notification 961, the 304-point 4-layer pbga package dimensions for symbol aaa, coplanarity, are changed from maximum value 0.15 mm to maximum value 0.2 mm. 2. pci 2.3 compliance the pci special interest group ratified the pci version 2.3 specification. to meet new requirements, an additional bit was added in the command register and an additional bit added in the status register of the 21555 bridge. the new register bits information is presented in the ? documentation changes ? section of this specification update. 21555 non-transparent pci-to-pci bridge specification update 15 documentation changes specification clarifications 1. none for this revision of this specification update. 16 21555 non-transparent pci-to-pci bridge specification update documentation changes documentation changes 1. section 3.4.6: jtag timing specifications table 1 has been updated and now appears as follows: 2. section 4.0, table 16, 304-point 4-layer pbga package dimensions issue: the maximum value for symbol aaa, dimension coplanarity, has been changed from 0.15 mm to a value of 0.2 mm. affected docs: 21555 non-transparent pci-to-pci bridge advance information datasheet (278320) . 3. add a specific reference to 21554 to first introduction paragraph issue: refer to chapter 1, page 1-1, first paragraph, third sentence, first clause: change: ? a related peripheral device, ? to say ? the 21554, a related peripheral device, has a 64-bit primary interface, ? . the entire paragraph should appear as follows: ? intel ? s 21555 is a pci peripheral device that performs pci bridging functions for embedded and intelligent i/o applications. the 21555 has a 64-bit primary interface, a 64-bit secondary interface, and 66-mhz capability. the 21554 a related pci peripheral device, has a 64-bit primary interface, a 64-bit secondary interface, and 33-mhz capability. ? affected docs: 21555 non-transparent pci-to-pci bridge advance information user?s manual (278321). table 1. jtag timing specifications symbol parameter minimum maximum unit t jr tck frequency 0 5 mhz t jp tck period 200 ns t ght tck high time 100 ? ns t glt tck low time 100 ? ns t jrt tck rise time 1 1. measured between 0.8 v and 2.0 v. ? 10 ns t gft tck fall time 2 2. measured between 2.0 v and 0.8 v. ? 10 ns t js tdi, tms setup time to tck rising edge 10 ? ns t jh tdi, tms hold time from tck rising edge 25 ? ns t jd tdo valid delay from tck falling edge 3 3. c 1 =50 pf. affected docs: 21555 non-transparent pci-to-pci bridge advance information datasheet (278320). ? 30 ns t jfd tdo float delay from tck falling edge ? 30 ns 21555 non-transparent pci-to-pci bridge specification update 17 documentation changes 4. remove sections 4.2 through 4.2.4 to section 2.3.4 issue: remove these sections: 4.2 64-bit operation the 21555 provides 64-bit extension support on the primary and secondary interfaces. both 64-bit and 32-bit operation are supported on both interfaces. this section describes how to use the 64-bit extensions. it describes the conditions under which a transaction can be treated as a 64-bit transaction and includes information about how the transaction is forwarded. 4.2.1 address phase of 64-bit transactions when a transaction using the primary bus 64-bit extension is a single address cycle (sac) ? that is, the address falls below the 4gb boundary, and the upper 32 bits of the address are assumed to be zero ? ad<63:32> and c/be#<7:4> are not defined but are driven to valid logic level during the address phase. when the transaction is a dual address cycle (dac), that is, the address falls above the 4gb boundary and the upper 32 bits of the address are non-zero, signals ad<63:32> contain the upper 32 bits of the address for both address phases. signals c/be#<7:4> contain the memory bus command during both address phases. a 64-bit target then has the opportunity to decode the entire 64-bit address and bus command after the first address phase. a 32-bit target needs both address phases to decode the full address and bus command. 4.2.2 data phase of 64-bit transactions during memory write transactions, when the 21555 has driven req64# to indicate it is initiating a 64-bit transfer, the 21555 drives the following during the data phase: the low 32 bits of data on ad<31:0> the low four byte enable bits on c/be#<3:0> the high 32 bits of data on ad<63:32> the high four byte enable bits on c/be#<7:4> when the 21555 detects ack64# asserted by the target at the same time that it detects devsel# asserted, every data phase then consists of 64 bits and eight byte enable bits. for write transactions, when the 21555 does not detect ack64# asserted at the same time that it detects devsel# asserted, the 21555 redirects the write data that it has on the ad<63:32> bus to ad<31:0> during the second data phase. similarly, the upper four byte enable bits are redirected to c/be#<3:0> during the second data phase. all data phases then consist of 32 bits. for 64-bit memory write transactions that end at an odd dword boundary, the 21555 drives the byte enable bits to 1 during the last data phase. signals ad<63:32> are then unpredictable but are driven to a valid logic level. for read transactions, when the 21555 has asserted req64#, it drives 8 bits of byte enables on c/be#<7:0> . since the only read transactions that use the 64-bit extension are prefetchable memory read transactions, the byte enable bits are always zero. therefore, no special redirection is needed based on the target ? s assertion or lack of assertion of ack64# . when the target asserts ack64# at the same time that it asserts devsel# , all read data transfers then consist of 64 bits and the target drives par64 , which covers ad<63:32> and c/be#<7:4> . when the target does not assert ack64# when it asserts devsel# , all data phases then consist of 32 bits. 18 21555 non-transparent pci-to-pci bridge specification update documentation changes 4.2.3 64-bit transactions received by the 21555 when the 21555 is the target of a transaction and the 21555 detects req64# asserted during a memory transaction to be forwarded across the bridge, the 21555 either asserts ack64# at the same time that it asserts devsel# to indicate its ability to perform 64-bit data transfers. under certain circumstances, the 21555 does not use the 64-bit extension as a target and therefore does not assert ack64# . the 21555 does not assert ack64# when any of the following is true: signal req64# was not asserted by the initiator. the 21555 is responding to a non-prefetchable memory read transaction. the 21555 is responding to an i/o transaction. the 21555 is responding to a configuration transaction. only 1 dword of data was read from the target. when the 21555 is the target of a 64-bit memory write transaction, it is able to accept 64 bits of data during each data phase. when the 21555 is the target of a 64-bit prefetchable memory read transaction, it supplies 64 bits of read data during each data phase and drives par64 corresponding to ad<63:32> and c/be#<7:4> , for each data phase. when an odd number of dwords was read from the target and the 21555 has asserted ack64# when returning read data to the initiator, the 21555 disconnects before the last odd dword is returned. the 21555 may have read an odd number of dwords because of either a target disconnect or a master latency timer expiration during 32-bit data transfers on the opposite interface. 4.2.4 64-bit extension support during reset when the 21555 supports a 64-bit interface on its primary bus, it samples p_req64_l while p_rst_l is asserted to determine whether the pci 64-bit extension signals are connected on the board. when p_req64_l is high, the 64-bit extension signals are not connected and the 21555 drives the 64-bit extension outputs to have valid logic levels on the inputs. the 21555 treats all transactions on the primary interface as 32-bit transactions. when p_req64_l is low, the 64-bit signals are connected to pull-up resistors on the board and the 21555 does not perform any input biasing. in this case, the 21555 can treat memory write and prefetchable memory read transactions as 64-bit transactions on the primary interface, as previously described in this section. the 21555 always asserts s_req64_l low during s_rst_l assertion to indicate that the 64-bit extension is supported on the secondary bus. individual pull-up resistors must always be supplied for s_ad<63:32 >, s_cbe_l<7:4 >, and s_par6 4. affected docs: 21555 non-transparent pci-to-pci bridge advance information user ? s manual (278321) . 21555 non-transparent pci-to-pci bridge specification update 19 documentation changes 5. remove unnecessary parenthetical phrase from rom interface signal description issue: refer to section 6.1, table 6-1, page 6-2. under pr_ad[6], remove from the last sentence: ? (if implemented). ? affected docs: 21555 non-transparent pci-to-pci bridge advance information user ? s manual (278321). 6. table 10-1 p_clk and s_clk descriptions need correction and updating issue: refer to table 10-1, pages 10-1 and 10-2, the last sentences in the p_clk and s_clk signal name descriptions. the sentences are inaccurate. the paragraphs below contain the corrected sentences. affected docs: 21555 non-transparent pci-to-pci bridge advance information user ? s manual (278321). 7. section 11.2.1, hot insertion input pin description change issue: refer to section 11.2.1, on page 11-3, last paragraph. remove the last sentence that paragraph should appear as follows: ? the 21555 is selected to be the secondary bus central function when it detects pr_ad[6] low when s_rst_l is asserted. when the 21555 detects this condition, it immediately drives s_ad , s_cbe_l , and s_par low and tristates secondary bus control signals for the duration of secondary bus reset. when the 21555 implements a 64-bit secondary interface, it also asserts s_req64_l , but tristates all other secondary bus 64-bit extension signals. ? affected docs: 21555 non-transparent pci-to-pci bridge advance information user ? s manual (278321). 8. remove or change 3 incorrect references to the 21554 issue: the following three entries that refer to the 21554 were modified: page 9-3, table 9-3, row labeled ? downstream delayed read ? , change ? 21554 ? to ? 21555 ? . page 9-4, table 9-3, row labeled ? upstream delayed read ? , change ? 21554 ? to ? 21555 ? . section 11.3, page 11-4, end of step 3, remove ? (21554 only.) ? . affected docs: 21555 non-transparent pci-to-pci bridge advance information user ? s manual (278321). p_clk i primary interface pci clk. this signal provides timing for all transactions on the primary pci bus. all primary pci inputs are sampled on the rising edge of p_clk , and all primary pci outputs are driven from the rising edge of p_clk . the 21555 operates in a frequency range from 0 mhz to 66 mhz in synchronous mode. in asynchronous mode the 21555 supports a clocking ratio (defined p_clk : s_clk or s_clk : p_clk) of a maximum ratio 2.5 : 1 with the upper frequency limit for either clock input being 66mhz. s_clk i secondary interface pci clk. this signal provides timing for all transactions on the secondary pci bus. all secondary pci inputs are sampled on the rising edge of s_clk , and all secondary pci outputs are driven from the rising edge of s_clk . the 21555 operates in a frequency range from 0 mhz to 66 mhz in synchronous mode. in asynchronous mode the 21555 supports a clocking ratio (defined p_clk : s_clk or s_clk : p_clk) of a maximum ratio 2.5 : 1 with the upper frequency limit for either clock input being 66mhz 20 21555 non-transparent pci-to-pci bridge specification update documentation changes 9. section 16.1byte offset of d7:d6 needs updating issue: refer to section 16.1, table 16-1, on page 16-4, the d7:d6 byte offset register name and reset value row. add the following information to the register name and reset value (hex) columns. affected docs: 21555 non-transparent pci-to-pci bridge advance information user ? s manual (278321) . 10. remove reference to cls=4 issue: remove the following lines: section 2.3.1.4, page 2-14 delete ? a full cache line threshold is used for cls=4 ? . section 2.4.2.2, table 2-25, page 2-36. delete two sentences: ? when cls=4 a full cache line threshold is used. ? . affected docs: 21555 non-transparent pci-to-pci bridge advance information user ? s manual (278321) 11. jtag action during hot insertion issue: change table 12-1 row 3 to be as follows: affected docs: 21555 non-transparent pci-to-pci bridge advance information user manual (278321) . 12. internal and external signal terminations issue: change table 12-1 rows 1 and 4 to be as follows: affected docs: 21555 non-transparent pci-to-pci bridge advance information user manual (278321) . d5 secondary serr# disable 00 y y y d7:d6 mode settings configuration register determined by parallel rom strapping options ? ny db:d8 reset control 0000 ? primary y tms i the jtag test mode select pin, tms causes state transitions in the test access port (tap) controller. the tms signal is pulled high by a weak pull-up resistor internal to the device. if this pin is low while t_rst_l is low the device can enter an unsupported mode. other devices that are not on early power and are connected to the jtag scan chain, pull tms low during hot insertion causing the 21555 to enter the unsupported mode. during the hot insertion isolate this signal from other jtag devices on the circuit board or jtag scan chain. tck i jtag boundary-scan clock. signal tck is the jtag logic control clock. this pin has an internal weak pull-down resistor. trst_l i jtag tap reset and disable. when low, jtag is disabled and the tap controller is asynchronously forced into the reset state, which in turn asynchronously initializes other test logic. an unterminated trst_l is pulled high by a weak pull-up resistor internal to the device. the tap controller must be reset before the jtag circuits can function. for normal jtag tap port operation, this signal must be high. prior to normal 21555 operation, this signal must be strobed low or pulled low with a 1k ? resistor. 21555 non-transparent pci-to-pci bridge specification update 21 documentation changes 13. change to initialization section 12.2.1 and jtag description issue: change to second paragraph. also made a change to normal operation description note for jtag below figure 12-1. the section now appears as follows: 12.2.1 initialization the test access port controller and the instruction register output latches are initialized and jtag is disabled while the trst_l input is asserted low (see figure 12-1 ). while signal trst_l is low, the test access port controller enters the test-logic reset state. this results in the instruction register being reset which holds the bypass register instruction. during test-logic reset state, all jtag test logic is disabled, and the device performs normal functions. the test access port controller leaves this state only after trst_l (low) goes high and an appropriate jtag test operation sequence is sent on the tms and tck pins. for the 21555 to operate properly, the jtag logic must be reset. the controller resets: asynchronously with the assertion of trst_l . synchronously after five tck clock cycles, with tms held high. note: prior to normal 21555 operation, this signal must be strobed low or pulled low with a 1k ? affected docs: 21555 non-transparent pci-to-pci bridge advance information user manual (278321). 14. change to chapter 2, table 2-3 p_req64_l description issue: the last row of table 2-3 now appears as follows: affected docs: 21555 non-transparent pci-to-pci bridge advance information user manual (278321). figure 12-1. signal trst_l states p_req64_l sts primary pci interface request 64-bit transfer. signal p_req64_l is asserted by the initiator to indicate that the initiator is requesting 64-bit data transfer. signal p_req64_l has the same timing as p_frame_l. when deasserting, p_req64_l is driven to a deasserted state for one clock cycle and is then sustained by an external pull-up resistor. the 21555 samples p_req64_l during primary reset to enable the 64-bit extension signals. if p_req64_l is sampled high during primary reset, the primary 64-bit extension is disabled and assumed not connected. the 21555 then drives p_ad[63:32], p_cbe_l[7:4], and p_par64 to valid logic levels. note: refer to the rom interface signal pr_ad[1] description in chapter 6, table 6-1 for information on primary bus 64-bit extension operation upon deassertion of r_rst_in_l. a7805-01 trst_l jtag reset jtag enabled 22 21555 non-transparent pci-to-pci bridge specification update documentation changes 15. change to section 11.5 l_stat pin description issue: last bullet changed and last note removed. the last bullet now appears as follows: support bi-directional pin, l_stat. this signal functions as both a micro-switch sensor input and a led control output. 2 ms of debounce is built into the 21555 l_stat pin. affected docs: 21555 non-transparent pci-to-pci bridge advance information user manual (278321). 16. added section 3.1.1 pci local bus compliance issue: added section 3.1.1 that includes new bit information to meet pci local bus specification 2.3 requirements. the new section appears as follows: 3.1.1 added bits for pci local bus specification 2.3 compliance two bits were added to the 21555 bridge to meet pci local bus specification 2.3 requirements: bit 10 in the command registers and bit 3 in the status registers. the a3 stepping of the bridge now includes these new features. note: for a description of the added bits, please refer to the 21555 non-transparent pci-to-pci bridge advance information user ? s manual. affected docs: 21555 non-transparent pci-to-pci bridge datasheet (278320) . 17. change to tables 61 and 62 in section 16.5.2 issue: two bits were added to the 21555 bridge to meet pci local bus specification 2.3 requirements. as a result, bit 10 information was added to table 61 in section 16.5.2 in the command registers and bit 3 information was added to table 62 in section 16.5.2 in the status registers. the a3 stepping of the bridge now includes these new features. the new information appears in the tables as follows: table 61. primary and secondary command registers bit name r/w description 10 1 1. bit not used and does not apply to step a2 of product interrupt disable bit r/w this bit disables the 21555 from asserting p_inta_l / s_inta_l. when 0, enables the 21555 to assert its p_inta_l / s_inta_l signal. when 1, disables the 21555 ability to assert the p_inta_l / s_inta_l signal. this bit ? s state after rst# is 0. offsets primary command secondary command primary byte 05:04h 45:44h secondary byte 45:44h 05:04h 21555 non-transparent pci-to-pci bridge specification update 23 documentation changes affected docs: 21555 non-transparent pci-to-pci bridge advance information user manual (278321). table 62. primary and secondary status registers bit name r/w description 3 1 1. bit not used and does not apply to step a2 of product interrupt status bit r this bit reflects the state of the interrupt in the 21555 bridge. only when the interrupt disable bit in the command register is set to 0 and the appropriate interrupt status bit set to 1 will the p_inta_l/s_inta_l signals be asserted. setting the interrupt disable bit to a 1 has no effect on the state of this bit. offsets primary status secondary status primary byte 07:06h 47:46h secondary byte 47:46h 07:06h 21555aa/ba and 21555ab/bb differences application note october 2002 order number: 278669-001 ii application note information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel?s website at http://www.intel.com. intel is a trademark or registered trademark of intel corporation or its subsidiaries in the united states and other countries. copyright ? intel corporation, 2002 *other names and brands may be claimed as the property of others. application note iii contents contents 1.0 introduction ............................................................................................................................... 5 1.1 changes to the 21555 bridge ............................................................................................... 5 2.0 stepping differences ............................................................................................................. 5 3.0 i2o asynchronous operation ............................................................................................. 5 4.0 bsdl data being driven late ............................................................................................ 6 5.0 new feature - pci 2.3 compliance ................................................................................... 6 21555aa/ba and 21555ab/bb differences application note 5 1.0 introduction this document defines the differences between the 21555aa/ba bridge when compared with the 21555ab/bb bridge. the 21555 bridge is a second generation non-transparent pci-to-pci bridge. 1.1 changes to the 21555 bridge after the introduction of the 21555aa/ba bridge, two errata were discovered ? the i 2 o circuitry would not work in asynchronous mode. the bsdl circuitry was driving data one cycle late. additionally, the pci standards committee ratified the new pci 2.3 specification, which required an additional bit to be added to the control register and status register. the new 21555ab/bb bridge version addresses all three of these issues. note: this differences document is not a stand-alone document and does not provide complete 21555 bridge details. the intent here is only to highlight the feature differences between the 21555aa/ba and the 21555ba/bb steppings. please be sure to review the data sheet and spec updates for more complete information on the device. 2.0 stepping differences table 1. stepping differences 3.0 i2o asynchronous operation the 21555aa/ba devices would not operate asynchronously. this behavior has been corrected in the 21555ab/bb device. please refer to the device data sheet for information on i 2 o operation. package markings rev_id register value a a. identified in a pci system by reading the value in the rev_id register. speed (mhz) stepping intel fw21555aa 02h 33 a2 intel fw21555ba 02h 66 a2 intel FW21555AB 03h 33 a3 intel fw21555bb 03h 66 a3 21555aa/ba and 21555ab/bb differences 6 application note 4.0 bsdl data being driven late the 21555aa/ba bsdl (boundary-scan description language) data was being driven one clock cycle late causing a potential device contention issue if bsdl was single stepped during testing. this behavior has been corrected in the 21555ab/bb device. the bsdl file does not change. 5.0 new feature - pci 2.3 compliance the pci special interest group ratified the pci 2.3 specification requiring an additional bit in the control register and an additional bit in the status register. the new register bits are as follows: note: please refer to the following documentation for more information: 21555 non-transparent pci-to-pci bridge datasheet 21555 non-transparent pci-to-pci bridge user?s manual 21555 non-transparent pci-to-pci bridge hardware implementation manual 21555 specification update table 1. primary and secondary command registers bit name r/w description 10 interrupt disable bit r/w this bit disables the 21555 from asserting p_inta_l / s_inta_l. when 0, enables the 21555 to assert its p_inta_l / s_inta_l signal. when 1, disables the 21555 ability to assert the p_inta_l / s_inta_l signal. this bit ? s state after rst# is 0. offsets primary command secondary command primary byte 05:04h 45:44h secondary byte 45:44h 05:04h table 2. primary and secondary status registers bit name r/w description 3 interrupt status bit r this bit reflects the state of the interrupt in the 21555 bridge. only when the interrupt disable bit in the command register is set to 0 and the appropriate interrupt status bit set to 1 will the p_inta_l/s_inta_l signals be asserted. setting the interrupt disable bit to a 1 has no effect on the state of this bit. offsets primary status secondary status primary byte 07:06h 47:46h secondary byte 47:46h 07:06h |
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